{"title":"A military avionics 32-bit advance modular processor system","authors":"D. R. Witzel","doi":"10.1109/DASC.1990.111333","DOIUrl":"https://doi.org/10.1109/DASC.1990.111333","url":null,"abstract":"A high-performance processor architecture embedded in a modular computer system with advanced application software real-time operating system support is discussed. The objective is to provide a powerful processing environment to satisfy the computational demands of data fusion and other expansion potentials of the avionics mission function. The processor engine of this system is the AMP (advanced modular processor), an extremely powerful 32-b embedded 20 MIPS processor deriving its performance from the MIPS R3000/R3010 RISC chip set. The distributed system architecture integrates multiple processors, a flexible I/O subsystem, and fault-tolerant features. A dual-redundant VME-like backplane and reconfiguration through reassignment of hot spare processors greatly increases reliability and availability. Consideration is given to the hardware system architecture, the external interfaces, the semiconductor technology, the real-time operating system, and the application software development.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134015331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Lala, R. Harper, K. R. Jaskowiak, G. Rosch, L. Alger, A. Schor
{"title":"Advanced Information Processing System (AIPS)-based fault tolerant avionics architecture for launch vehicles","authors":"J. Lala, R. Harper, K. R. Jaskowiak, G. Rosch, L. Alger, A. Schor","doi":"10.1109/DASC.1990.111274","DOIUrl":"https://doi.org/10.1109/DASC.1990.111274","url":null,"abstract":"An avionics architecture for the advanced launch system (ALS) that uses validated hardware and software building blocks developed under the advanced information processing system program is presented. The AIPS for ALS architecture is preliminary, and reliability requirements can be met by the AIPS hardware and software building blocks that are built using the state-of-the-art technology available in the 1992-3 time frame. The level of detail in the architecture definition reflects the level of detail available in the ALS requirements. As the avionics requirements are refined, the architecture can also be refined and defined in greater detail with the help of analysis and simulation tools. A useful methodology is demonstrated for investigating the impact of the avionics suite to the recurring cost of the ALS. It is shown that allowing the vehicle to launch with selected detected failures can potentially reduce the recurring launch costs. A comparative analysis shows that validated fault-tolerant avionics built out of Class B parts can result in lower life-cycle-cost in comparison to simplex avionics built out of Class S parts or other redundant architectures.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129503399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated toolset for high-integrity system verification and validation support (avionics)","authors":"R.P. Cabos","doi":"10.1109/DASC.1990.111298","DOIUrl":"https://doi.org/10.1109/DASC.1990.111298","url":null,"abstract":"The basic principles and underlying design of a toolset for high-integrity system verification and validation support are presented. First experiences in the application of the toolset to an avionics software maintenance project are discussed. An outline is given of work, which features the extension of the existing toolset to a certification support system.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130999276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Artificial intelligence programming in Ada","authors":"K.R. Leeper","doi":"10.1109/DASC.1990.111279","DOIUrl":"https://doi.org/10.1109/DASC.1990.111279","url":null,"abstract":"The Boeing Advanced Blackboard Ada Generation Environment (BABBAGE), a development environment with an associated toolset intended for specific blackboard paradigm, is presented. BABBAGE will provide a means of rapidly defining, implementing, debugging, maintaining, and documenting an artificial intelligence program in Ada. Topics discussed are the intended functionality of the environment, the relationship of the environment to the Ada language, and the current development status.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126209051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fault tolerant fly by wire system for maintenance free applications","authors":"R. Dennis, A. Hills","doi":"10.1109/DASC.1990.111255","DOIUrl":"https://doi.org/10.1109/DASC.1990.111255","url":null,"abstract":"The authors describe a triplex primary flight computer system based on a reconfigurable architecture with extensive use of application specific integrated circuits (ASICs). The system comprises fault-tolerant fly-by-wire (FBW) computers which are triplex dissimilar in both software and hardware. These command actuator control electronics (ACE) units via DATAC (ARINC 629) data buses. The FBW computers form the core of the full-authority FBW system and perform all the computational commands for the pitch, roll, and yaw surface actuation systems. The authors review the architectural design issues in terms of integrity requirements and fault tolerance, leading to a design which not only meets civil safety requirements but also has ultra-high-reliability, offering little or no maintenance action. The FBW computer architecture is based on dividing the basic path into three subfunctional elements. Each of these elements is then replicated to provide fault tolerance. The internal element redundancy management function is performed both in hardware and software, and it is able to detect and isolate faulty elements and perform the necessary reconfiguration. The current expectation for system reliability gives an expected time to 95% probability of dispatch of 38100 operating hours and has a predicted MTBMA of 92700 operating hours per shipset.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129140383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Content addressable memory for electronic warfare sensor signature identification","authors":"L. P. Butler, J.E. Meisenbacher","doi":"10.1109/DASC.1990.111284","DOIUrl":"https://doi.org/10.1109/DASC.1990.111284","url":null,"abstract":"It is proposed that content addressable memory (CAM) can be used to reduce or eliminate the pattern identification bottleneck in EW (electronic warfare) systems. CAM may be used to perform all or part of this identification function in parallel across all known patterns in a pulse data buffer within a few machine cycles. Initial analysis using CAM in the pattern bit-byte recognition operations of the processing has identified a possible four to one gain in processing responses for this function under current data set characteristics. This gain is realized when CAM is used for partial identification. A possible eight to one gain in processing may be achieved when total identification is performed by the CAM device. It is pointed out that the expected increase in size and complexity of future systems tends to improve the advantages of systems which use CAM technology.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129153200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated code generation for application engineers (avionics)","authors":"J.J. Turkovich","doi":"10.1109/DASC.1990.111358","DOIUrl":"https://doi.org/10.1109/DASC.1990.111358","url":null,"abstract":"An approach which generates code and documentation from specifications of application designs is described. This approach to code generation is realistic, realizable with current technology, and capable of dramatically increasing productivity and reliability in avionics systems. The ALS CASE system, which adheres to this approach, has been implemented and used to successfully generate approximately 3000 lines of Ada code from a specification of a Boeing 737 autoland flight control system.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126867797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Validation of the F-18 high alpha research vehicle flight control and avionics systems modifications","authors":"V. Chacon, J. Pahle, V.A. Regenie","doi":"10.1109/DASC.1990.111254","DOIUrl":"https://doi.org/10.1109/DASC.1990.111254","url":null,"abstract":"The authors discuss the tests, tools, and techniques used for the validation of the F-18 high alpha research vehicle (HARV) turning vane control system (TVCS), and document the problems and their solutions. The HARV system modification to add a research flight control system (RFCS) and TVCS included the integration of avionics, engine parameters, and external inputs into the flight control system. This integration introduced flexible experimental components into the system. The validation of the HARV system modification included many aspects. The system design included the capability to extract internal parameters from the control system. The interface between the RFCS and the basic F-18 system contained checks and balances to ensure that the safety of the total system was not compromised by unforeseen circumstances. The testing addressed critical issues to ensure the backup system was not compromised by the addition of the experimental systems. The integrated test facility systems were used to automate repetitive tests and collect large amounts of data, and allowed the test team to concentrate on interpreting test results rather than the test system. The test team encountered problems with the system under test with the inability to sort through the information in an efficient manner, to maintain communications over large distances, and to obtain desired results in a timely manner.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126948876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A threshold redundancy management algorithm for skewed sensor arrays","authors":"F. E. DeAngelis","doi":"10.1109/DASC.1990.111275","DOIUrl":"https://doi.org/10.1109/DASC.1990.111275","url":null,"abstract":"A thresholdless algorithm for redundancy management that can be used to obtain specified failure tolerance for a given SRIMU (skewed redundant inertial measurement unit) is presented. The algorithm is an extension of some earlier work by J.E. Potter and M.C. Suman (1986), which presented a method for implementing threshold less (FDI) (fault detection and isolation) on a pentad skewed sensor array. The proposed algorithm overcomes the single-failure-tolerance restriction of Potter's algorithm, and allows thresholdless FDI to be practically implemented on a hexad or higher order array. Some performance results are given which compare a hexad IMU, under a particular failure scenario, with no FDI algorithm, a threshold FDI algorithm, and the thresholdless FDI algorithm. The performance of the thresholdless FDI algorithm is seen to be comparable to that of the threshold FDI algorithm for the particular launch vehicle trajectory. Thus, comparable performance to threshold FDI algorithms may be attained by the thresholdless algorithm without the additional complexity of threshold determination.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117256216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Pegasus avionics system design","authors":"D.A. Steffy","doi":"10.1109/DASC.1990.111309","DOIUrl":"https://doi.org/10.1109/DASC.1990.111309","url":null,"abstract":"The Pegasus air-launched space booster successfully completed its maiden flight on April 5, 1990. Many recent advances in digital avionics and computer technology simplified the vehicle and its testing. The single-string Pegasus avionics comprise multiple microcontroller-based remote units for controlling actuators, firing thrusters and pyrotechnics, and gathering telemetry arranged in a serial digital star network centered on the VMEBUS flight computer. Flight, aircraft, and test software is in C, with small amounts of FORTH and assembly language. A series of laboratory, simulation, mobile test bed, motor static firing, and captive flight tests verified that the avionics system was ready for free flight.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129014368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}