7th International Symposium on Quality Electronic Design (ISQED'06)最新文献_第2页

On optimizing scan testing power and routing cost in scan chain design 扫描链设计中扫描测试功率和路由成本的优化

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.95

L. Hsu, Hung-Ming Chen

{"title":"On optimizing scan testing power and routing cost in scan chain design","authors":"L. Hsu, Hung-Ming Chen","doi":"10.1109/ISQED.2006.95","DOIUrl":"https://doi.org/10.1109/ISQED.2006.95","url":null,"abstract":"With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present an approach to simultaneously minimizing power and routing cost in scan chain reordering after cell placement. We formulate the problem as a traveling salesman problem (TSP), different cost evaluation from (Bonhomme et al., 2004), (Bonhomme et al., 2003), and apply an efficient heuristic to solve it. The experimental results are encouraging. Compared with a recent result in (Bonhomme et al., 2004), which uses the approach with clustering overhead, we obtain up to 10% average power saving under the same low routing cost Furthermore, we obtain 57% routing cost improvement under the same test power consumption in s9234, one of ISCAS'89 benchmarks. We collaborate multiple scan chains architecture with our methodology and obtain good results as well","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128105235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Robust dynamic node low voltage swing domino logic with multiple threshold voltages 具有多个阈值电压的鲁棒动态节点低压摇摆多米诺逻辑

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.112

Zhiyu Liu, V. Kursun

{"title":"Robust dynamic node low voltage swing domino logic with multiple threshold voltages","authors":"Zhiyu Liu, V. Kursun","doi":"10.1109/ISQED.2006.112","DOIUrl":"https://doi.org/10.1109/ISQED.2006.112","url":null,"abstract":"A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power consumption and enhancing evaluation speed and noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at inputs and outputs for robust and high speed operation. Power supply, ground, and threshold voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 51.9% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 40.4% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the evaluation speed and noise immunity are enhanced by up to 19.4% and 39.1%, respectively, as compared to the standard full-swing circuits. The proposed low swing technique also reduces the idle mode leakage power consumption of high fan-in domino gates by up to 84.2%","PeriodicalId":138839,"journal":{"name":"7th International Symposium on Quality Electronic Design (ISQED'06)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131511348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Reducing the data switching activity on serial link buses 减少串行链路总线上的数据交换活动

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.111

M. Ghoneima, Y. Ismail, M. Khellah, V. De

引用次数: 18

On N-detect pattern set optimization 关于n检测模式集的优化

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.94

Yu Huang

引用次数: 31

Compiler-directed power density reduction in NoC-based multicore designs 基于cpu的多核设计中编译器导向的功率密度降低

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.36

S. Narayanan, M. Kandemir, O. Ozturk

引用次数: 11

Thermal trends in emerging technologies 新兴技术的热趋势

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.136

G. Link, N. Vijaykrishnan

引用次数: 76

Enabling quality and schedule predictability in SoC design using HandoffQC 使用HandoffQC实现SoC设计的质量和进度可预测性

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.59

Bhaskar J. Karmakar, V. Chakravarty, R. Venkatraman, J. Rao

引用次数: 1

Structure synthesis of analog and mixed-signal circuits using partition techniques 利用分划技术进行模拟和混合信号电路的结构合成

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.125

K. Zeng, S. Huss

引用次数: 2

LOTUS: leakage optimization under timing uncertainty for standard-cell designs LOTUS:时间不确定条件下标准电池设计的泄漏优化

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.83

Sarvesh Bhardwaj, Yu Cao, S. Vrudhula

引用次数: 8

A technique for estimating the difficulty of a formal verification problem 一种估计形式化验证问题难度的技术

7th International Symposium on Quality Electronic Design (ISQED'06) Pub Date : 2006-03-27 DOI: 10.1109/ISQED.2006.17

Indradeep Ghosh, M. Prasad

引用次数: 2