2016 17th Latin-American Test Symposium (LATS)最新文献

{"title":"Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables","authors":"Serhiy Avramenko, M. Reorda, M. Violante, G. Fey","doi":"10.1109/LATW.2016.7483332","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483332","url":null,"abstract":"Data logging applications, such as those deployed in satellite launchers to acquire telemetry data, may require compression algorithms to cope with large amounts of data as well as limited storage and communication capabilities. When commercial-off-the-shelf hardware components are used to implement such applications, radiation-induced soft errors may occur, especially during the last stages of the launcher cruise, potentially affecting the algorithm execution. The purpose of this work is to analyze two compression algorithms using fault injection to evaluate their robustness against soft errors. The main contribution of the work is the analysis of the compression algorithm susceptibility by attacking their data structures (also referred as program variables) rather than the memory elements of the computing platform in charge of the algorithm execution. This approach is agnostic of the downstream implementation details. Instead, the intrinsic robustness of compression algorithms can be evaluated quickly, and system-level decisions can be taken before the computing platform is finalized.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gate-level modelling of NBTI-induced delays under process variations","authors":"T. Copetti, Guilherme Medeiros Machado, L. Poehls, F. Vargas, S. Kostin, M. Jenihhin, J. Raik, R. Ubar","doi":"10.1109/LATW.2016.7483343","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483343","url":null,"abstract":"Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). Moreover, the impact of NBTI is exacerbated by Process Variation (PV), i.e. variations on transistor attributes during the manufacturing process. In this paper, a hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed. The model is applied in order to identify NBTI-critical logic paths of ICs that are subject to aging mitigation techniques. The model is derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. The experimental results demonstrate an accurate fitting between the analysis performed on the proposed gate-level model and the electrical simulations, while the gate-level analysis provides for several orders of magnitude speed-up in simulation.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122837213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Auxiliary IP blocks for early dependability analysis of small processor based systems","authors":"J. Barboza, J. Basualdo, J. P. Acle","doi":"10.1109/LATW.2016.7483334","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483334","url":null,"abstract":"Fault injection experiments are a powerful aid to identify and fix problems in the design of fault tolerance mechanisms, particularly when performed at early development phases. For this purpose, it is important not only to classify the faults, but also to understand the different faulty behaviors. When an embedded system is considered, a common approach for analyzing the faulty behavior is to exploit the execution trace features often available in medium to high size processors. This paper proposes two IP modules intended to facilitate fault injection experiments in small processor systems: a memory saboteur and a bus event recorder. The former allows the injection of SEU and stuck-at faults, both at a specific memory location and at the address or data bus level. The latter provides an alternative to the use of a full execution trace solution, which is often not available in small processors. The IP blocks were used to inject the faults and to analyze the behavior of a submodule of an implantable pulse generator running on an FPGA-hosted openMSP430 processor system. The IP blocks, the fault injection environment and the results of the fault injection campaigns are presented. The event traces captured by the event recorder IP played a fundamental role to understand the faulty behavior.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134256805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Known unknowns — Knowledge in the presence of unknowns","authors":"B. Becker","doi":"10.1109/LATW.2016.7483328","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483328","url":null,"abstract":"With ever increasing complexities and a component-based design style there is a growing number of unknowns (e.g., at the interface of components) and their handling becomes more and more important in electronic design automation (EDA) and production processes. Methods and tools are required that in principle allow a modeling of unknowns balancing between exactness of representation and efficiency of calculation. We highlight state-of-the-art approaches that enable an efficient and successful integration of unknown values using formal techniques in the areas of Test and Verification/Validation.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124125979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A methodology for early functional verification of embedded software combining virtual platforms and bounded model checking","authors":"Rogério Paludo, D. Lettnin","doi":"10.1109/LATW.2016.7483354","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483354","url":null,"abstract":"The amount of embedded software present in our daily routines has been increasing with more electronic devices being introduced in many different areas. As a consequence, concerns with safety and reliability has led to the development of a series of mechanisms for verification and design of such systems. Although Bounded model checking (BMC), for example, has received much attention lately, practical use might be restricted, considering systems complexity. In this paper, we show a methodology for combining BMC with Electronic System Level Design and Virtual Platforms. Our approach has the potential to improve system level verification, through simulation, and to accelerate the development process with Virtual Platforms.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131502759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processors","authors":"Mario Schölzel, T. Koal, Sebastian Müller, S. Scharoba, Stephanie Roder, H. Vierhaus","doi":"10.1109/LATW.2016.7483336","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483336","url":null,"abstract":"The integration of a diagnostic software-based self-test and a software-based self-repair method into a single statically scheduled superscalar processor is presented. The self-test method is used as start-up test in-the-field in order to detect and localize permanent faults in the processor. The determined fault state is handed over to a software-based self-repair program. This program adapts the user application, which should be executed on the core, to the current fault state. Thereby both methods are able to cope with multiple permanent faults in the core. For this purpose the self-test programs as well as the self-repair program can be adapted to the current fault state, too. The paper also describes the diagnostic capability of the self-test programs and the achieved fault coverage. The hardware and program memory overhead for the self-test and self-repair programs is reported, too.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130294330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comprehensive approach to fault tolerance: Device, circuit, and system techniques","authors":"Z. Stamenkovic, V. Petrovic","doi":"10.1109/LATW.2016.7483333","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483333","url":null,"abstract":"Summary form only given. In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. This work presents a design methodology for fault-tolerant ASIC that is based on radiation-hard technology, redundant circuits with latchup protection, additional implementation steps during logic synthesis and layout generation, and power gating. Enhancements have been made within the standard ASIC design flow in order to incorporate redundancy and power-switch cells and, consequently, enable protection against single-event upset (SEU), single-event transient (SET), and single-event latchup (SEL). In order to validate the proposed fault-tolerant circuits, a fault-injection environment including fault models has been developed. The fault occurrence and its duration are modeled according to the real effects in actual hardware. Some of these techniques are being exploited and implemented in the SEPHY project (http://www.sephy.eu), which aims to increase the European competitiveness in the field of fault-tolerant ASIC by developing a radiation-hard PHY layer of the 10/100-Base-T Ethernet transceiver. The radiation-hard PHY layer ASIC will be fabricated in Atmel's 150 nm technology. This device will enable the use of Ethernet in space systems and also provide the base to implement a radiation-hard Gigabit Ethernet PHY layer for space applications. Additionally, the developed techniques and devices can be of interest in other critical applications like automotive or industrial systems. In order to automate a design flow of the fault-tolerant circuits, it is essential to design specific cells which are notpresent in the standard or radiation-hard design kits. A SEL protection switch (SPS) is described first. It consists of a current sensor/driver, feedback block, control block, and communication interface for a power network controller. Afterwards, the details of triple-modular redundant (TMR) and double-modular redundant (DMR) circuits with latchup protection and separated power domains are presented. Fault-injection models for TMR and DMR circuits are developed in order to simulate and verify the fault-tolerant designs. Functional simulation of a digital design at the gate level suffices in case of the single-event transient and upset effects. However, in order to provide the information about design behavior during latchup effect, it is required to functionally simulate the design at the transistor level. We present the TMR and DMR circuit simulation results with the implemented fault-injection models for all three types of the mentioned single-event effects. Fault-tolerant ASICs can be implemented using the standard design automation tools and introducing a few additional steps in the standard design flow. An extra step is necessary to generate a modified design netlist including redundant cells, voters and required protection f","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130063956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accessing on-chip instruments through the life-time of systems","authors":"E. Larsson, Farrokh Ghani Zadegan","doi":"10.1109/LATW.2016.7483327","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483327","url":null,"abstract":"The electronic systems we find in almost every product today are implemented using integrated circuits (ICs) mounted on printed circuit boards (PCBs). Developing electronic systems is a challenging task due to complexity and miniaturization. A single IC can contain billions of transistors, which are smaller than ever. As a result more Design-for-Test (DfT) features, so called instruments, are embedded on-chip in modern ICs to handle and monitor various activities. Many defects are handled at IC manufacturing; however, there are many problems occurring after ICs are being mounted on PCBs. In many cases, it is unfortunately not possible to reproduce the problem when the electronic system is taken to a repair shop. These problems are known as No Trouble Found (NTF). One obstacle is the limited access to the on-chip DfT instruments that exist in most ICs. We will discuss access to on-chip DfT instruments through the life-time of electronic systems. We will focus on electronic systems using the IEEE 1687 standard.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124216258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dependability evaluation of COTS microprocessors via on-chip debugging facilities","authors":"José Isaza-González, A. Serrano-Cases, Felipe Restrepo-Calle, S. Cuenca-Asensi, A. Martínez-Álvarez","doi":"10.1109/LATW.2016.7483335","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483335","url":null,"abstract":"This paper presents a fault injection system for performing fault injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. The proposed system takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility and flexibility of the proposal as a low-cost solution for assessing the reliability of COTS microprocessors.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124604350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spin transfer torque memories for on-chip caches: Prospects and perspectives","authors":"Akhilesh R. Jaiswal, K. Roy","doi":"10.1109/LATW.2016.7483330","DOIUrl":"https://doi.org/10.1109/LATW.2016.7483330","url":null,"abstract":"Non-volatile memories based on electron spin have potential to be the future universal memory technology, owing to zero leakage, high density, almost unlimited endurance and acceptable dynamic power consumption. In this article, we present device, circuit and architectural solutions to mitigate some of the challenges associated with spin-transfer-torque magnetic random access memories (STT-MRAMs), for example, the statistical nature of switching, high write energy consumption and susceptibility to parametric process variations. The proposed design methods at various levels of abstraction improves the overall robustness, energy consumption as well as density of STT-MRAMs for on chip memory applications.","PeriodicalId":135851,"journal":{"name":"2016 17th Latin-American Test Symposium (LATS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121089115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}