2018 IEEE East-West Design & Test Symposium (EWDTS)最新文献_第5页

Development of Time-Varying PLL Macromodel for Jitter Evaluation 用于抖动评估的时变锁相环宏模型的开发

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524678

M. Gourary, S. Rusakov, S. Ulyanov, M. Zharov

引用次数: 0

Evolution of a Problem of the Hidden Faults in the Digital Components of Safety-Related Systens 安全相关系统数字组件中隐藏故障问题的演变

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524806

A. Drozd, M. Kuznietsov, S. Antoshchuk, Alexander N. Martynyuk, M. Drozd, Y. Sulima

{"title":"Evolution of a Problem of the Hidden Faults in the Digital Components of Safety-Related Systens","authors":"A. Drozd, M. Kuznietsov, S. Antoshchuk, Alexander N. Martynyuk, M. Drozd, Y. Sulima","doi":"10.1109/EWDTS.2018.8524806","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524806","url":null,"abstract":"This paper is devoted to a problem of the hidden faults which is shown in digital components of the safety-related systems aimed at providing of the functional safety of objects with the increased risk. These systems are considered on the basis of resource approach as development of computer systems with diversification of an operating mode by its division on normal and emergency. The problem consists in accumulation of faults throughout a continuous normal mode in absence of the input data showing them. In the most responsible emergency mode, accumulated faults are shown in lowering of fault tolerance on which the functional safety is based. The problem of the hidden faults is identified as a problem in development of resources where diversification of a checkability of the circuits contradicts designing of the digital components at the bottom level of resource development - replication. Problem solutions by increase in the level of resource development in designing of the digital components, including a method of a choice of the version in program codes of the FPGA project are suggested.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":" 979","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113946597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Image Search by Content System Development 基于内容系统开发的图像搜索

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524602

Valentina Potapova, A.Yu. Tarasov, N. Grinchenko

引用次数: 2

Algorithm for Separating GNSS Signals into Components GNSS信号分块算法

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524708

Alexey Malvshev, Ivan Malav, M. Ozerov

引用次数: 3

Compact Four-Stub Coupler 紧凑的四根耦合器

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524671

D. Letavin, V. Chechetkin, Y. Mitelman

引用次数: 1

An FPGA-Optimized Architecture of Variational Optical Flow 变分光流的fpga优化结构

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524759

P. Belyakov, M. Nikiforov

引用次数: 2

Cryogenic Operational Amplifier on Complementary JFETs 互补型jfet的低温运算放大器

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524640

O. Dvornikov, N. Prokopenko, A. Bugakova, V. Tchekhovski, I. Maliy

引用次数: 15

Circuit Partitioning Problem Clustering Method Based on Adjacency Matrix Unification 基于邻接矩阵统一的电路划分问题聚类方法

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524668

V. Kureichik, I. Safronenkova

{"title":"Circuit Partitioning Problem Clustering Method Based on Adjacency Matrix Unification","authors":"V. Kureichik, I. Safronenkova","doi":"10.1109/EWDTS.2018.8524668","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524668","url":null,"abstract":"The present work deals with artificial intelligence research. The problem of engineering software benchmarking study for the purpose of fitting for task type and computational resources is important today. This problem is often solved by the help of intelligence decision support systems (IDSS). Domain ontology is a typical knowledge representation model in such systems. Manual ontology development is a time-consuming and expensive process. Because of a great variety of circuit partitioning problem formulization, clustering is a necessary step of automated circuit partitioning problem ontology development. The problem of automated circuit partitioning problem clustering appears because of integrated data comparison. This data is represented by different dimension structures. The goal of this work is the development of circuit partitioning problem clustering method based on adjacency matrix unification. The hypergraph model of circuit representation was chosen, circuit partitioning problem was formalized. The case of adjacency matrix with different dimension clustering was observed. The novelty of proposed method is the inclusion of matrix with different dimension unification procedure in the generic clustering method.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127437068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Wearable Artificial Kidney Design Principles 可穿戴人工肾脏设计原理

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524761

N. Bazaev, B. M. Putrya, N. Zhilo, V. Grinval'd

引用次数: 0

A Journey from STIL to Verilog 从still到Verilog的旅程

2018 IEEE East-West Design & Test Symposium (EWDTS) Pub Date : 2018-09-01 DOI: 10.1109/EWDTS.2018.8524673

Slimane Boutobza, Sorin Popa, Andrea Costa

{"title":"A Journey from STIL to Verilog","authors":"Slimane Boutobza, Sorin Popa, Andrea Costa","doi":"10.1109/EWDTS.2018.8524673","DOIUrl":"https://doi.org/10.1109/EWDTS.2018.8524673","url":null,"abstract":"With the growing complexity of System-On-Chips (SoCs), and the explosion of test data volume, test patterns validation is becoming a mandatory and crucial step. With modern large designs, detecting most issues at the level of the ATE is no longer a viable solution. Recent approaches rely on dedicated tools and flows prior to tester to validate test patterns, and reserve ATE to only screening real defect issues on the test-chip. This allows for early detection of successive and cumulative modeling and processing steps. In [1] we presented an original simulation-based patterns validation approach. A crucial step in that approach was the translation from cycle-based tester domain to an event-based simulation domain. This paper focuses on that part by presenting an approach for efficient and trustful translation of a STIL file to an equivalent HDL (Verilog) representation. To the best of our knowledge, this is the first paper that describes a full and detailed tester based language (STIL) to an HDL (Verilog) translation, thereby expressing fully and accurately the behavior of cycle based domain into an event-based environment. Such transformation allows porting the problem from tester domain to HDL and logic simulation domain, and exploiting their capabilities for sake of efficient validation, but also, debug, coverage and functional tests. The proposed approach is an industry proven methodology that was successfully implemented and exploited by an EDA tool [2] that is now used by several semiconductors companies for their daily pattern validation flows.","PeriodicalId":127240,"journal":{"name":"2018 IEEE East-West Design & Test Symposium (EWDTS)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2