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Dual work function high-k/Metal Gate CMOS FinFETs 双工作功能高k/金属栅极CMOS finfet
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430915
M. Hussain, C. Smith, P. Kalra, Ji-Woon Yang, G. Gebara, B. Sassman, P. Kirsch, P. Majhi, S. Song, R. Harris, H. Tseng, R. Jammy
{"title":"Dual work function high-k/Metal Gate CMOS FinFETs","authors":"M. Hussain, C. Smith, P. Kalra, Ji-Woon Yang, G. Gebara, B. Sassman, P. Kirsch, P. Majhi, S. Song, R. Harris, H. Tseng, R. Jammy","doi":"10.1109/ESSDERC.2007.4430915","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430915","url":null,"abstract":"For the first time, a set of complementary metal oxide semiconductor (CMOS) FinFET devices with two different high-k/metal gate stacks of dual work function has been integrated on the same wafer to overcome the integration complexity. Two completely different metals deposited by atomic layer deposition have been integrated in a process that includes gate stack integration and dual metal gate etch. Excellent short channel characteristics with low drain induced barrier lowering (DIBL) and subthreshold swing DeltaSS have been observed with fairly symmetric VTh.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and characterization of STI compatible high-voltage NMOS and PMOS devices in standard CMOS process 在标准CMOS制程中，STI相容高压NMOS与PMOS元件的设计与表征
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430907
Xiaolian Han, Chihao Xu
{"title":"Design and characterization of STI compatible high-voltage NMOS and PMOS devices in standard CMOS process","authors":"Xiaolian Han, Chihao Xu","doi":"10.1109/ESSDERC.2007.4430907","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430907","url":null,"abstract":"This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25 mum/5 V CMOS process technology. Breakdown voltages of 35 V for n-channel with a specific on resistance of 1.96 mOmega.cm2 and -45 V for p-channel with a specific on-resistance of 8.73 mOmega.cm2 have been achieved without any modification of existing standard CMOS process.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126949472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Germanium-On-Nothing (GeON): an innovative technology for ultrathin Ge film integration 无锗(GeON):超薄锗薄膜集成的创新技术
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430975
E. Batail, S. Monfray, D. Rideau, M. Szczap, N. Loubet, T. Skotnicki, C. Tabone, J. Hartmann, S. Borel, G. Rabillé, J. Damlencourt, B. Vincent, B. Previtali, L. Clavelier
{"title":"Germanium-On-Nothing (GeON): an innovative technology for ultrathin Ge film integration","authors":"E. Batail, S. Monfray, D. Rideau, M. Szczap, N. Loubet, T. Skotnicki, C. Tabone, J. Hartmann, S. Borel, G. Rabillé, J. Damlencourt, B. Vincent, B. Previtali, L. Clavelier","doi":"10.1109/ESSDERC.2007.4430975","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430975","url":null,"abstract":"In this paper, a novel CMOS device concept called Germanium-On-Nothing (GeON) is proposed. GeON allows integration of ultrathin Ge films on insulator on a conventional Si substrate. In particular we demonstrate the realization of 20 nm-thick Si0.06Ge0.94 films on 15 nm buried dielectric. In the second part of the paper, simulations were performed to highlight the advantages of ultrathin body Ge devices on Insulator. The resulting TCAD simulations coupled with an original quantum confinement model show that reducing the Ge thickness below 7 nm leads to enhanced electrostatic integrity compared to its Si counterparts.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129006510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Multi-gate devices for the 32nm technology node and beyond 用于32nm及以上技术节点的多栅极器件
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430899
N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B. Pawlak, R. Rooyackers, T. Schulz, K.T. Sar, N. Son, M. V. van Dal, P. Verheyen, K. von Arnim, L. Witters, De Meyer, S. Biesemans, M. Jurczak
{"title":"Multi-gate devices for the 32nm technology node and beyond","authors":"N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B. Pawlak, R. Rooyackers, T. Schulz, K.T. Sar, N. Son, M. V. van Dal, P. Verheyen, K. von Arnim, L. Witters, De Meyer, S. Biesemans, M. Jurczak","doi":"10.1109/ESSDERC.2007.4430899","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430899","url":null,"abstract":"Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121785198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era 横向扩展(LatEx)主动用于改善60纳米以下DRAM时代的数据保留时间
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430944
Sungsam Lee, Jong-Woo Park, Kwangwook Lee, S. Jang, Junhong Lee, H. Byun, Ilgweon Kim, Yongjin Choi, M.S. Shim, D. Song, Joosung Park, Tae-woo Lee, D.W. Shin, G. Jin, Kinam Kim
{"title":"Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era","authors":"Sungsam Lee, Jong-Woo Park, Kwangwook Lee, S. Jang, Junhong Lee, H. Byun, Ilgweon Kim, Yongjin Choi, M.S. Shim, D. Song, Joosung Park, Tae-woo Lee, D.W. Shin, G. Jin, Kinam Kim","doi":"10.1109/ESSDERC.2007.4430944","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430944","url":null,"abstract":"A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126459668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Rigorous extraction of process variations for 65nm CMOS design 严格提取65nm CMOS设计的工艺变化
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430886
Wei Zhao, Yu Cao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka
{"title":"Rigorous extraction of process variations for 65nm CMOS design","authors":"Wei Zhao, Yu Cao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. Nowka","doi":"10.1109/ESSDERC.2007.4430886","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430886","url":null,"abstract":"Statistical circuit analysis and optimization are critical for robust nanoscale design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, we present a rigorous method to extract process variations from in-situ IV measurements. Transistor statistics are collected from a test chip fabricated in a 65 nm SOI process. We recognize gate length (L), threshold voltage (Vth) and mobility (mu) as the leading variation sources, due to the tremendous process challenge in lithography, channel doping, and stress. To decompose them, only three IV points are needed from the leakage and linear regions. Both L and Vth variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, we can accurately predict the change of drive current in all process corners. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126759075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
The role of inelastic electron-phonon interaction on the on-current and gate delay time of CNT FETs 非弹性电子-声子相互作用对碳纳米管场效应管通流和栅极延迟时间的影响
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430922
M. Pourfath, H. Kosina, S. Selberherr
{"title":"The role of inelastic electron-phonon interaction on the on-current and gate delay time of CNT FETs","authors":"M. Pourfath, H. Kosina, S. Selberherr","doi":"10.1109/ESSDERC.2007.4430922","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430922","url":null,"abstract":"The performance of carbon nanotube field-effect transistors is analyzed using the non-equilibrium Green's function formalism. The role of the inelastic electron-phonon interaction on both, on-current and gate delay time, is studied. For the calculation of the gate delay time the quasi-static approximation is assumed. The results confirm experimental data of carbon nanotube transistors, where the on-current can be close to the ballistic limit, but the gate delay time can be far below that limit.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126676151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effective control of flat-band voltage in HfO2 gate dielectric with La2O3 incorporation La2O3掺入对HfO2栅极介质平带电压的有效控制
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430913
K. Okamoto, M. Adachi, K. Kakushima, P. Ahmet, N. Sugii, K. Tsutsui, T. Hattori, H. Iwai
{"title":"Effective control of flat-band voltage in HfO2 gate dielectric with La2O3 incorporation","authors":"K. Okamoto, M. Adachi, K. Kakushima, P. Ahmet, N. Sugii, K. Tsutsui, T. Hattori, H. Iwai","doi":"10.1109/ESSDERC.2007.4430913","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430913","url":null,"abstract":"The origin of negative flat-band shift using La<sub>2</sub>O<sub>3</sub> incorporation in HfO<sub>2</sub> dielectrics has been extensively examined. From careful extraction of effective work function of gate electrode and fixed charges at each interface, it has been revealed that La<sub>2</sub>O<sub>3</sub> at high-k/Si substrate or high-k/SiO<sub>2</sub> interface has either large amount of positive fixed charges or an additional dipole of 0.36 V compared to that of HfO<sub>2</sub>/Si or HfO<sub>2</sub>/SiO<sub>2</sub>. Stacked MOSCAPs were fabricated and the C-V characteristics show that flat-band voltage shift is mainly determined by high-k film which is in contact to Si or SiO<sub>2</sub>. Using HfLaO with different La concentration, the amount of shift in flat-band voltage could be well controlled, which might be due to the diffusion or pile-up of La atoms to the interface over 420degC. This study provides further insights in controlling the threshold voltage of HfO<sub>2</sub> based oxides.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126944677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Characterization and modeling of CMOS on-chip coupled interconnects CMOS片上耦合互连的表征与建模
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430903
R. Kumar, S. Rustagi, Kai Kang, K. Mouthaan, T. Wong
{"title":"Characterization and modeling of CMOS on-chip coupled interconnects","authors":"R. Kumar, S. Rustagi, Kai Kang, K. Mouthaan, T. Wong","doi":"10.1109/ESSDERC.2007.4430903","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430903","url":null,"abstract":"In this paper, an S-parameter measurement based modeling methodology is proposed for characterization of coupled interconnects on silicon substrate. First, a set of single transmission lines in ground-signal-ground configuration is measured and modeled as multiple Gamma-sections. A pair of coupled lines is then modeled as two single lines interconnected by coupling capacitance, mutual inductance and mutual resistance. Asymptotic techniques and closed-form analytical expressions are used to determine the initial guesses for optimization of the model parameters of single and coupled lines. It is found that in extending the single line model to the coupled lines, only a couple of model parameters need to change due to the proximity effect. Further, the time-domain crosstalk is measured for Cu/oxide and Cu/Ultra low-kappa interconnects and analyzed using the proposed model. Good agreement is found between the simulated and measured results in both the frequency and the time domains for different lengths, widths and spacing (for coupled-lines) confirming the accuracy of the modeling methodology. The compact modeling approach presented here facilitates accurate characterization and modeling of coupled interconnects based on measured S-parameters data.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Anisotropy of electron mobility in arbitrarily oriented FinFETs 任意定向finfet中电子迁移率的各向异性
ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430957
F. Gámiz, L. Donetti, N. Rodriguez
{"title":"Anisotropy of electron mobility in arbitrarily oriented FinFETs","authors":"F. Gámiz, L. Donetti, N. Rodriguez","doi":"10.1109/ESSDERC.2007.4430957","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430957","url":null,"abstract":"We simulated the behavior of electron mobility and the effect of volume inversion in FinFETs with different surface (hkl) orientations and channel <hkl> directions, using a Monte Carlo simulator. For each surface orientation, different channel directions were also considered. In the case of the (110) surface, a strong anisotropy of electron mobility with channel direction was seen: when the channel was in the (110)/<001> direction, electron mobility was 50% higher than in (110)/<1-10>, and was similar to the mobility for a (100)/<001> direction. This anisotropic behavior with channel orientation was not observed in the (100)-or (111)-surface orientations. The study with silicon thickness also revealed some interesting consequences of the volume inversion effect.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"69 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113961563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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