Spatial: a language and compiler for application accelerators

D. Koeplinger, Matthew Feldman, R. Prabhakar, Yaqi Zhang, Stefan Hadjis, Ruben Fiszel, Tian Zhao, Luigi Nardi, A. Pedram, C. Kozyrakis, K. Olukotun
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引用次数: 155

Abstract

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for productivity and are difficult to target from higher level languages. HLS tools are more productive, but offer an ad-hoc mix of software and hardware abstractions which make performance optimizations difficult. In this work, we describe a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators. We describe Spatial's hardware-centric abstractions for both programmer productivity and design performance, and summarize the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning. We demonstrate the language's ability to target FPGAs and CGRAs from common source code. We show that applications written in Spatial are, on average, 42% shorter and achieve a mean speedup of 2.9x over SDAccel HLS when targeting a Xilinx UltraScale+ VU9P FPGA on an Amazon EC2 F1 instance.
空间:用于应用程序加速器的语言和编译器
工业越来越多地转向可重构架构,如fpga和CGRAs,以提高性能和能源效率。不幸的是,这些体系结构的采用受到其编程模型的限制。hdl缺乏对生产力的抽象,并且很难从高级语言中获得目标。HLS工具的生产效率更高,但提供了软件和硬件抽象的临时组合,这使得性能优化变得困难。在这项工作中,我们描述了一种新的领域特定语言和编译器,称为Spatial,用于对应用程序加速器进行更高级别的描述。我们描述了Spatial以硬件为中心的抽象,以提高程序员的工作效率和设计性能,并总结了支持这些抽象所需的编译器传递,包括流水线调度、自动内存银行和由主动机器学习驱动的自动设计调优。我们演示了该语言从通用源代码中针对fpga和CGRAs的能力。我们发现,在Amazon EC2 F1实例上使用Xilinx UltraScale+ VU9P FPGA时,用Spatial编写的应用程序比SDAccel HLS平均缩短了42%,平均加速提高了2.9倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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