A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-/spl mu/m CMOS technology

Abstract

This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 while dissipating 50 mW of power from a 3.3-V supply.