Mixed signal design of cascadable matched filters

Abstract

This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm/sup 2/ core by 0.8 /spl mu/m SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.