Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip

Abstract

To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by many-core processor chips, wireless Network-on-Chip (WiNoC) has been proposed by using the recently developed CMOS ultra wideband interconnection. In this research, we propose an unequal RF nodes overlaid mesh topology design to improve the on-chip communication performance. A network capacity model is developed for fast searching of optimal topology configuration. A high-efficient, low-cost zone-aided routing scheme is designed to facilitate deadlock freedom. The simulation study demonstrates topology modeling effectiveness, routing efficiency, and promising network performance of the overlaid mesh WiNoC over a regular 2D mesh baseline.