Self-timed statistical carry lookahead adder using multiple-output DCVSL

Abstract

We show that an efficient implementation of a self-timed statistical carry lookahead adder can be built from a Manchester carry chain. By exploiting multiple-output DCVSL, the presented implementation not only relieves the delay matching problem of previous design in completion detection but also reduces the number of transistors. The worst case delay is comparable to the previous design, and 25.8% of average power consumption is reduced.