Bit-Level Systolic Arrays for Digital Contour Smoothing by Abel-Poisson Kernel

IF 0.5 Q4 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS

Parallel Processing Letters Pub Date : 1993-03-01 DOI:10.1142/S0129626493000071

J. Glasa

引用次数: 2

Abstract

Two different bit-level systolic arrays for digital contour smoothing by Abel-Poisson kernel which minimize the execution time and the number of functional elements required are suggested. The arrays are fully pipelined on the bit-level achieving very high clock frequency. They are implementable in VLSI and are dedicated for real-time applications.

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Abel-Poisson核数字轮廓平滑的位级收缩阵列

提出了两种不同的位级收缩阵列，以最大限度地减少执行时间和所需功能元素的数量。这些阵列在位级上完全流水线化，实现了非常高的时钟频率。它们可在VLSI中实现，并专门用于实时应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Parallel Processing Letters COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS-

CiteScore

0.90

自引率

25.00%

发文量

期刊介绍： Parallel Processing Letters (PPL) aims to rapidly disseminate results on a worldwide basis in the field of parallel processing in the form of short papers. It fills the need for an information vehicle which can convey recent achievements and further the exchange of scientific information in the field. This journal has a wide scope and topics covered included: - design and analysis of parallel and distributed algorithms - theory of parallel computation - parallel programming languages - parallel programming environments - parallel architectures and VLSI circuits