The Mirage of Breaking MIRAGE: Analyzing the Modeling Pitfalls in Emerging “Attacks” on MIRAGE

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-07-21 DOI:10.1109/LCA.2023.3297875

Gururaj Saileshwar;Moinuddin Qureshi

引用次数: 0

Abstract

This letter studies common modeling pitfalls in security analyses of hardware defenses to highlight the importance of accurate reproduction of defenses. We provide a case study of MIRAGE (Saileshwar and Qureshi 2021), a defense against cache side channel attacks, and analyze its incorrect modeling in a recent work (Chakraborty et al., 2023) that claimed to break its security. We highlight several modeling pitfalls that can invalidate the security properties of any defense including a) incomplete modeling of components critical for security, b) usage of random number generators that are insufficiently random, and c) initialization of system to improbable states, leading to an incorrect conclusion of a vulnerability, and show how these modeling bugs incorrectly cause set conflicts to be observed in a recent work’s (Chakraborty et al., 2023) model of MIRAGE. We also provide an implementation addressing these bugs that does not incur set-conflicts, highlighting that MIRAGE is still unbroken.

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打破海市蜃楼的海市蜃楼:分析海市蜃楼新出现的“攻击”中的建模缺陷

本文研究了硬件防御安全分析中常见的建模缺陷，以强调准确复制防御的重要性。我们提供了MIRAGE的案例研究(Saileshwar和Qureshi 2021)，这是一种针对缓存侧通道攻击的防御，并在最近的一项工作(Chakraborty等人，2023)中分析了其错误的建模，该工作声称破坏了其安全性。我们强调了几个可以使任何防御的安全属性无效的建模缺陷，包括a)对安全至关重要的组件的不完整建模，b)使用随机数生成器的随机性不足，以及c)将系统初始化到不可能的状态，导致对漏洞的错误结论，并展示了这些建模错误如何在最近的工作(Chakraborty et al.， 2023) MIRAGE模型中观察到的集合冲突。我们还提供了一个解决这些错误的实现，它不会引起集合冲突，强调MIRAGE仍然是未被破坏的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.