Highly Robust All-Oxide Transistors Toward Vertical Logic and Memory

Abstract

In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In2O3 as the conducting gate, and ALD In2O3 thin film itself serves as source/drain contacts to the ALD In2O3 channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over $400~^{\circ }$ C but also gained a boosted on-/off-ratio over $10^{{7}}$ with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability ( $\boldsymbol {\Delta } {V}_{\text {TH}}\text {)}$ of −5 and −50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for $10^{{4}}$ s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In2O3 with thickness as well as gate length ( ${T}_{\text {IO,{g}}}\text {)}$ of 10 nm, achieving on-/off-ratio over $10^{{5}}$ and maximum current ( ${I}_{\max }\text {)}$ over $160~\boldsymbol {\mu } $ A/ $\boldsymbol {\mu } $ m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to $10^{{12}}$ cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.