Theoretical Threshold Voltage of Two-Dimensional Semiconductor Field-Effect Transistors

Abstract

Using two-dimensional (2D) semiconductors as channel materials of field-effect transistors (FETs) has made significant advances in recent years. However, the relevant theory lags behind experiment. For example, the current–voltage relationship for 3D FET devices has still been used to analyze the performance parameters of 2D FETs. Here, we reexamine the relationship for 3D FETs and find that the concept of threshold voltage in it is not valid for 2D ones because 2D channel semiconductors with atomic-level thickness do not have the concept of surface potential used to define the threshold voltage of 3D FETs. From the current–voltage relationship derived by us for 2D back-gate FETs, the theoretical expression of the 2D threshold voltage is extracted, which describes a particular gate voltage that causes a 2D channel material going into the critical state of degeneracy, and it depends on the parameters such as the ideal work-affinity difference, the net charge in the oxide, and the applied drain voltage. The relevant experimental data also support our theoretical definition of the threshold voltage. The parameters present in the 2D threshold voltage can provide theoretical guidance on the modulation of the threshold voltage of 2D FETs.