Impact of Top SiO₂ Interlayer Thickness on Memory Window of Si Channel FeFET With TiN/SiO₂/Hf₀.₅Zr₀.₅O₂/SiOx/Si (MIFIS) Gate Structure

Abstract

We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/ Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. Meanwhile, we study the impact of the top SiO2 interlayer thickness on the retention characteristics of the MIFIS structure. The results of retention characteristics show that the MIFIS structure with thicker top SiO2 has poorer retention characteristics. This is attributed to the de-trapping of interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface and the depolarization field of the ferroelectric. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.