Optimizing delay and energy in 4-bit absolute-value detector circuits: A balancing act

Abstract

This research focuses on optimizing the 4-bit absolute-value detector circuit. This paper firstly introduces the basic theory of the circuit as the foundation of the analysis. It contains the function, logic and the theories which are used in the design. Secondly, this paper optimizes the circuit from two perspective, which are the delay and the energy. This research aims to find the relation between these two factors. Furthermore, because the delay and the energy are both critical to the performance of the circuit, and the conditions that determine one of the two factors also affect the other, this research also attempts to find a balance point which can optimize them as much as possible. In the end, this paper summarizes the result about the optimization and analyses the deficiencies of the experiment methods. This paper also gives suggestions about the perspective that the further studies can focus on in order to optimize the 4-bit absolute-value detector in a deeper degree.