GS-MDC: High-Speed and Area-Efficient Number Theoretic Transform Design

Abstract

Homomorphic encryption (HE) has recently become a promising approach to guarantee the privacy security in cloud computing. Number theoretic transform (NTT) can be used to accelerate the polynomial multiplication in HE, but is usually considered the performance bottleneck of HE schemes. This brief introduces GS-MDC, a high-speed and area-efficient NTT design combining multi-path delay commutator (MDC) architecture and GS butterfly units (GS-BUs). Exploiting the characteristics of GS-BU, a novel permute-in-computation (PiC) technique is proposed to reduce total computing cycles. GS-MDC is also designed to be reconfigurable for both NTT and INTT. Moreover, we put forward a hybrid storage method for twiddle factors to promote memory utilization efficiency. Experimental results on FPGA show that our design can achieve higher throughput and area efficiency compared with previous works.