Xiaofeng Ye , Huihuang Ke , Shubo Wei , Hongjin Weng , Xinwei Wang , Shen Yuong Wong , Weifeng Yang
{"title":"A trench beside field limiting rings terminal for improved 4H-SiC junction barrier Schottky diodes: Proposal and investigation","authors":"Xiaofeng Ye , Huihuang Ke , Shubo Wei , Hongjin Weng , Xinwei Wang , Shen Yuong Wong , Weifeng Yang","doi":"10.1016/j.microrel.2024.115459","DOIUrl":null,"url":null,"abstract":"<div><p>A novel trench beside field limiting rings (TBFLR) terminal for 4H-SiC junction barrier Schottky (JBS) diodes is introduced and analyzed by technical computer-aided design (TCAD) simulation, addressing the electric field crowding challenge in high-voltage applications. The design parameters of the devices are optimized by striking a balance between forward and reverse electrical performances. Comparative analysis reveals that TBFLR significantly reduces the surface peak electric field, making it particularly advantageous for shallow-junction devices. Conversely, trench inside FLR (TFLR) is suited for deep-junction applications due to its deeper junction and higher breakdown voltage (BV). The TBFLR design excels with its low on-resistance and compact terminal length, especially in ultra-high voltage (>6500 V) scenarios, achieving target BV with fewer rings and reduced terminal area. Notably, the TBFLR has a terminal efficiency of at least 80 % while keeping trench depth within the 60 % range of the junction depth. Furthermore, an enhanced computational model is proposed, which introduces harmonic parameters to quantify the role of the trench in FLR, and this adaptable model can be effectively extended to the composite renewal of FLR structures. This work provides a distinct application strategy for trench-based FLR structures, significantly broadening the scope of terminal design possibilities.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115459"},"PeriodicalIF":1.6000,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424001392","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel trench beside field limiting rings (TBFLR) terminal for 4H-SiC junction barrier Schottky (JBS) diodes is introduced and analyzed by technical computer-aided design (TCAD) simulation, addressing the electric field crowding challenge in high-voltage applications. The design parameters of the devices are optimized by striking a balance between forward and reverse electrical performances. Comparative analysis reveals that TBFLR significantly reduces the surface peak electric field, making it particularly advantageous for shallow-junction devices. Conversely, trench inside FLR (TFLR) is suited for deep-junction applications due to its deeper junction and higher breakdown voltage (BV). The TBFLR design excels with its low on-resistance and compact terminal length, especially in ultra-high voltage (>6500 V) scenarios, achieving target BV with fewer rings and reduced terminal area. Notably, the TBFLR has a terminal efficiency of at least 80 % while keeping trench depth within the 60 % range of the junction depth. Furthermore, an enhanced computational model is proposed, which introduces harmonic parameters to quantify the role of the trench in FLR, and this adaptable model can be effectively extended to the composite renewal of FLR structures. This work provides a distinct application strategy for trench-based FLR structures, significantly broadening the scope of terminal design possibilities.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.