Toward Finding S-Box Circuits With Optimal Multiplicative Complexity

IF 3.6 2区 计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Yongjin Jeon;Seungjun Baek;Jongsung Kim
{"title":"Toward Finding S-Box Circuits With Optimal Multiplicative Complexity","authors":"Yongjin Jeon;Seungjun Baek;Jongsung Kim","doi":"10.1109/TC.2024.3398507","DOIUrl":null,"url":null,"abstract":"In this paper, we present a new method to find S-box circuits with optimal multiplicative complexity (MC), i.e., MC-optimal S-box circuits. We provide new observations for efficiently constructing circuits and computing MC, combined with a popular pathfinding algorithm named A*. In our search, the A* algorithm outputs a path of length MC, corresponding to an MC-optimal circuit. Based on an in-depth analysis of the process of computing MC, we enable the A* algorithm to function within our graph to investigate a wider range of S-boxes than existing methods such as the SAT-solver-based tool \n<xref>[1]</xref>\n and \n<monospace>LIGHTER</monospace>\n \n<xref>[2]</xref>\n. We provide implementable MC-optimal circuits for all the quadratic 5-bit bijective S-boxes and existing 5-bit almost-perfect nonlinear (APN) S-boxes. Furthermore, we present MC-optimal circuits for 6-bit S-boxes such as Sarkar Gold, Sarkar Quadratic, and some quadratic permutations. Finally, we theoretically demonstrate new lower bounds for the MCs of S-boxes, providing tighter bounds for the MCs of \n<monospace>AES</monospace>\n and \n<monospace>MISTY</monospace>\n S-boxes than previously known. This study complements previous results on MC-optimal S-box circuits and is intended to provide further insight into this field.","PeriodicalId":13087,"journal":{"name":"IEEE Transactions on Computers","volume":"73 8","pages":"2036-2050"},"PeriodicalIF":3.6000,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Computers","FirstCategoryId":"94","ListUrlMain":"https://ieeexplore.ieee.org/document/10528277/","RegionNum":2,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
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Abstract

In this paper, we present a new method to find S-box circuits with optimal multiplicative complexity (MC), i.e., MC-optimal S-box circuits. We provide new observations for efficiently constructing circuits and computing MC, combined with a popular pathfinding algorithm named A*. In our search, the A* algorithm outputs a path of length MC, corresponding to an MC-optimal circuit. Based on an in-depth analysis of the process of computing MC, we enable the A* algorithm to function within our graph to investigate a wider range of S-boxes than existing methods such as the SAT-solver-based tool [1] and LIGHTER [2] . We provide implementable MC-optimal circuits for all the quadratic 5-bit bijective S-boxes and existing 5-bit almost-perfect nonlinear (APN) S-boxes. Furthermore, we present MC-optimal circuits for 6-bit S-boxes such as Sarkar Gold, Sarkar Quadratic, and some quadratic permutations. Finally, we theoretically demonstrate new lower bounds for the MCs of S-boxes, providing tighter bounds for the MCs of AES and MISTY S-boxes than previously known. This study complements previous results on MC-optimal S-box circuits and is intended to provide further insight into this field.
寻找具有最佳乘法复杂性的 S-Box 电路
在本文中,我们提出了一种寻找具有最优乘法复杂度(MC)的 S-box 电路(即 MC-最优 S-box 电路)的新方法。我们为高效构建电路和计算 MC 提供了新的观测方法,并结合了一种名为 A* 的流行寻路算法。在我们的搜索中,A* 算法会输出一条长度为 MC 的路径,与 MC 最佳电路相对应。基于对 MC 计算过程的深入分析,与基于 SAT 求解器的工具 [1] 和 LIGHTER [2] 等现有方法相比,我们使 A* 算法在我们的图中能够研究更广泛的 S 框。我们为所有二次 5 位双射 S-box 和现有的 5 位几乎完全非线性 (APN) S-box 提供了可实现的 MC 最佳电路。此外,我们还提出了 6 位 S-box 的 MC 最佳电路,如 Sarkar Gold、Sarkar Quadratic 和一些二次排列。最后,我们从理论上证明了 S-box 的 MC 的新下限,为 AES 和 MISTY S-box 的 MC 提供了比以前已知的更严格的下限。这项研究补充了之前关于 MC 最佳 S-box 电路的结果,旨在为这一领域提供更深入的见解。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
IEEE Transactions on Computers
IEEE Transactions on Computers 工程技术-工程:电子与电气
CiteScore
6.60
自引率
5.40%
发文量
199
审稿时长
6.0 months
期刊介绍: The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field. It publishes papers on research in areas of current interest to the readers. These areas include, but are not limited to, the following: a) computer organizations and architectures; b) operating systems, software systems, and communication protocols; c) real-time systems and embedded systems; d) digital devices, computer components, and interconnection networks; e) specification, design, prototyping, and testing methods and tools; f) performance, fault tolerance, reliability, security, and testability; g) case studies and experimental and theoretical evaluations; and h) new and important applications and trends.
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