SiC Super-Junction MOSFET robustness assessment and method to improve avalanche capability

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2024-05-09 DOI:10.1016/j.microrel.2024.115418

De-Xin Chen , Ying Wang , Yan-Xing Song , Xin-Xing Fei , Hao Huang

{"title":"SiC Super-Junction MOSFET robustness assessment and method to improve avalanche capability","authors":"De-Xin Chen , Ying Wang , Yan-Xing Song , Xin-Xing Fei , Hao Huang","doi":"10.1016/j.microrel.2024.115418","DOIUrl":null,"url":null,"abstract":"<div><p>In this paper, the reliability of super-junction MOSFET under single-pulse Unclamped Inductive Switching (UIS) was simulated using Sentaurus TCAD software. Through simulation of etching source metal, it was proved that the conduction of parasitic bipolar transistor in parallel multi-cell structure is the main cause of temperature concentration leading to burnout. The method of reinforcing super-junction MOSFET is proposed by using the conduction of parasitic transistors as the criterion for evaluating UIS performance. In the proposed two-layer alternating PN column stack structure, the upper PN columns have a charge imbalance structure with a higher p-column concentration than the n-column. The simulation results show that the improved structure has higher avalanche energy and wider process variation range compared to the traditional structure. Compared with the traditional device, the improved device achieves a continuous avalanche duration of 1.3 × 10<sup>−3</sup> s and an avalanche robustness of 8.24 joules (J) when the parasitic bipolar transistor is non-conductive, significantly reducing the process difficulty by increasing the P-base concentration deviation to 5.8 × 10<sup>17</sup> cm<sup>−3</sup> under the same avalanche duration range.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115418"},"PeriodicalIF":1.6000,"publicationDate":"2024-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424000982","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

In this paper, the reliability of super-junction MOSFET under single-pulse Unclamped Inductive Switching (UIS) was simulated using Sentaurus TCAD software. Through simulation of etching source metal, it was proved that the conduction of parasitic bipolar transistor in parallel multi-cell structure is the main cause of temperature concentration leading to burnout. The method of reinforcing super-junction MOSFET is proposed by using the conduction of parasitic transistors as the criterion for evaluating UIS performance. In the proposed two-layer alternating PN column stack structure, the upper PN columns have a charge imbalance structure with a higher p-column concentration than the n-column. The simulation results show that the improved structure has higher avalanche energy and wider process variation range compared to the traditional structure. Compared with the traditional device, the improved device achieves a continuous avalanche duration of 1.3 × 10⁻³ s and an avalanche robustness of 8.24 joules (J) when the parasitic bipolar transistor is non-conductive, significantly reducing the process difficulty by increasing the P-base concentration deviation to 5.8 × 10¹⁷ cm⁻³ under the same avalanche duration range.

查看原文本刊更多论文

碳化硅超级结 MOSFET 鲁棒性评估和提高雪崩能力的方法

本文使用 Sentaurus TCAD 软件模拟了单脉冲无钳位感应开关（UIS）下超级结 MOSFET 的可靠性。通过蚀刻源金属的仿真，证明了并联多单元结构中寄生双极晶体管的导通是导致烧毁的温度集中的主要原因。通过将寄生晶体管的传导作为评估 UIS 性能的标准，提出了强化超级结 MOSFET 的方法。在所提出的两层交替 PN 柱堆栈结构中，上层 PN 柱具有电荷不平衡结构，p 柱浓度高于 n 柱。仿真结果表明，与传统结构相比，改进后的结构具有更高的雪崩能量和更宽的工艺变化范围。与传统器件相比，改进后的器件在寄生双极晶体管不导电的情况下，雪崩持续时间为 1.3 × 10-3 s，雪崩稳健性为 8.24 焦耳 (J)，在相同的雪崩持续时间范围内，将 P 碱浓度偏差提高到 5.8 × 1017 cm-3，大大降低了工艺难度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.