An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits

Abstract

Parsing value change dump (VCD) files through signal turnover behavior is important for power analysis and estimation. In practical applications, the size of VCD files can reach hundreds of GB. Thus, designing an efficient VCD parser for parsing large VCD files is of great significance. Different from the traditional hash search functions applied in many VCD parsers, this letter proposes a specific search algorithm based on the rules of identifiers in VCD files. Then, a high-performance VCD parser is constructed. The parser supports single-core and multicore modes. Based on the regression test, the function of the VCD parser is verified. Experimental results show that the proposed VCD parser is faster and more functional than the vcd2saif. In multicore mode, our VCD parser only takes about 8.139 s to parse 1-GB VCD files, and the time consumption of the search algorithm only accounts for 2% of the total CPU time.