Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion

IF 2.8 3区计算机科学 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Micro Pub Date : 2024-01-26 DOI:10.1109/mm.2024.3358861

KyungSoo Lee, Sohyun Kim, Joohee Lee, Donguk Moon, Rakie Kim, Honggyu Kim, Hyeongtak Ji, Yunjeong Mun, Youngpyo Joo

引用次数: 0

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利用异构内存分层提高键值缓存性能：基于 CXL 的内存扩展案例研究

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Micro 工程技术-计算机：软件工程

CiteScore

7.50

自引率

0.00%

发文量

164

审稿时长

>12 weeks

期刊介绍： IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems. Contributions should relate to the design, performance, or application of microprocessors and microcomputers. Tutorials, review papers, and discussions are also welcome. Sample topic areas include architecture, communications, data acquisition, control, hardware and software design/implementation, algorithms (including program listings), digital signal processing, microprocessor support hardware, operating systems, computer aided design, languages, application software, and development systems.