A reference sampling ΔΣ subsampling PLL

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-01-25 DOI:10.1016/j.vlsi.2024.102160

Debdut Biswas

引用次数: 0

Abstract

In this work, a new subsampling PLL is presented which samples the reference signal by the oscillator’s phase and then again by the divided oscillator phase. The operation is robust due to the action of a frequency divider in the loop. Fractional synthesis can also be easily implemented by modifying the loop containing the frequency divider using a $Δ Σ$ modulator. Post-layout simulations are performed in CMOS 90 nm technology with a 1 GHz ring oscillator. Peak-to-peak jitter over 1000 cycles of the free running ring oscillator is 87 ps. It is reduced to 28 ps through the action of the proposed architecture.

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参考采样 ΔΣ 子采样 PLL

本研究提出了一种新型子采样 PLL，它通过振荡器相位对参考信号进行采样，然后再通过分频振荡器相位对参考信号进行采样。由于在环路中使用了分频器，因此运行非常稳定。通过使用 ΔΣ 调制器修改包含分频器的环路，也可以轻松实现分数合成。布局后仿真采用 CMOS 90 纳米技术，使用 1 GHz 环形振荡器。自由运行环形振荡器 1000 个周期的峰峰抖动为 87 ps。通过采用建议的架构，抖动降低到 28 ps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.