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Performance Analysis of a Generic Modular Adder via RTL Programming and IP Modeling Techniques on FPGA

Q3 Computer Science
Ingenierie des Systemes d''Information Pub Date : 2023-10-31 DOI:10.18280/isi.280514
Tukur Gupta, Gaurav Verma, Shamim Akhter
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Abstract

ABSTRACT
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基于FPGA RTL编程和IP建模技术的通用模块化加法器性能分析
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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来源期刊
Ingenierie des Systemes d''Information
Ingenierie des Systemes d''Information Computer Science-Information Systems
CiteScore
2.50
自引率
0.00%
发文量
84
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