C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse

Abstract

In this article, we propose a Complementary Deep-Neural-Network (C-DNN) processor V2 by optimizing the performance improvement from combination of CNN and SNN. C-DNN V1 showcased the potential for achieving higher energy efficiency by combining CNN and SNN. However, it encountered 5 challenges that hindered the full realization of this potential: Inefficiency of the clock gating accumulator, imbalance in spike sparsity across different time-steps, redundant cache power stemming from temporal weight reuse, limited performance of the SNN core for dense spike trains, and nonoptimal operation resulting from tile-based workload division. To overcome these challenges and achieve enhanced energy efficiency through the CNN-SNN combination, C-DNN V2 is developed. It addresses these challenges by implementing a Full-Adder/OR-based reduction tree, which reduces power consumption in the SNN core under high spike sparsity conditions. Additionally, it efficiently manages spike sparsity imbalances between dense and sparse SNN cores by integrating them simultaneously. The proposed reconfigurable spatial weight reuse method decreases the number of redundant register files and their power consumption. The spike flipping and inhibition method facilitate efficient processing of input data with high spike sparsity in the SNN core. Furthermore, fine-grained workload division and a high sparsity-aware CNN core are introduced to ensure optimal processing of each data in the domain with the highest energy efficiency. In conclusion, we propose the C-DNN V2 as an optimal complementary DNN processor, delivering 76.9% accuracy for ImageNet classification with a state-of-the-art energy efficiency of 32.8 TOPS/W.