Performance Enhancement of CNFET-based Approximate Compressor for Error Resilient Image Processing

Swetha Siliveri, Dr. N. Siva Sankara Reddy
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Abstract

The approximate computing has emerged as an appealing approach to minimize energy consumption. By implementing inexact circuits at the transistor level, significant enhancements in various performance metrics such as power consumption, delay, energy, and area can be achieved. Consequently, researchers worldwide have been actively exploring the application of inexact techniques in circuit design. This paper introduces a novel technique for designing low-power digital circuits called extremely low power modified gate diffusion input (ELP-MGDI). This technique combines the principles of Modified Gate Diffusion Input with the utilization of Carbon Nano Tube Field-Effect Transistors (CNTFETs). The Objective of this paper is to enhance the power, delay, and area characteristics of a 4:2 compressor and multiplier by employing ELP-MGDI approach. To achieve this, we conducted thorough analysis and simulations using the Verilog-A simulator 32 nm CNFET technology Stanford University within the Cadence Virtuoso Tool. The results show extremely power, delay reduction and power-delay-product (PDP) of approximate multiplier has been improved by over 99%, and the circuit area has been reduced by 55%. The proposed processing module demonstrates superior performance compared to their conventional counterparts.
基于cnfet近似压缩器的抗误差图像处理性能增强
近似计算已经成为最小化能源消耗的一种有吸引力的方法。通过在晶体管级实现不精确的电路,可以实现各种性能指标(如功耗、延迟、能量和面积)的显著增强。因此,世界各地的研究人员一直在积极探索不精确技术在电路设计中的应用。本文介绍了一种设计低功耗数字电路的新技术——极低功耗修正门扩散输入(ELP-MGDI)。该技术结合了改良栅扩散输入原理和碳纳米管场效应晶体管(cntfet)。本文的目的是利用ELP-MGDI方法提高4:2压缩乘法器的功率、延迟和面积特性。为了实现这一目标,我们在Cadence Virtuoso工具中使用斯坦福大学的Verilog-A模拟器32纳米CNFET技术进行了彻底的分析和模拟。结果表明,近似乘法器的极功耗、时延降低和功率延迟积(PDP)提高了99%以上,电路面积缩小了55%。与传统的处理模块相比,所提出的处理模块表现出优越的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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