Architectural Implications of GNN Aggregation Programming Abstractions

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-10-19 DOI:10.1109/LCA.2023.3326170

Yingjie Qi;Jianlei Yang;Ao Zhou;Tong Qiao;Chunming Hu

引用次数: 0

Abstract

Graph neural networks (GNNs) have gained significant popularity due to the powerful capability to extract useful representations from graph data. As the need for efficient GNN computation intensifies, a variety of programming abstractions designed for optimizing GNN Aggregation have emerged to facilitate acceleration. However, there is no comprehensive evaluation and analysis upon existing abstractions, thus no clear consensus on which approach is better. In this letter, we classify existing programming abstractions for GNN Aggregation by the dimension of data organization and propagation method. By constructing these abstractions on a state-of-the-art GNN library, we perform a thorough and detailed characterization study to compare their performance and efficiency, and provide several insights on future GNN acceleration based on our analysis.

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GNN 聚合编程抽象的架构影响

图形神经网络（GNN）具有从图形数据中提取有用表征的强大功能，因此大受欢迎。随着高效 GNN 计算需求的增加，出现了各种旨在优化 GNN 聚合的编程抽象，以促进 GNN 的加速。然而，目前还没有对现有抽象进行全面评估和分析，因此对于哪种方法更好还没有明确的共识。在这封信中，我们从数据组织和传播方法两个维度对现有的 GNN 聚合编程抽象进行了分类。通过在最先进的 GNN 库上构建这些抽象，我们进行了深入细致的特性研究，比较了它们的性能和效率，并根据我们的分析为未来的 GNN 加速提供了一些启示。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.