Toward reconfigurable associative architecture for high speed communication operators

Abstract

The renewed interest in the new associative organization is driven by advances in technologies and the increase in the need for intelligent and real-time application complexity, based on complex data structures. This paper presents a novel and practical architecture pointing to the feasibility of a structured addressable associative memory related to high speed communication protocols. This organization provides a maximum of flexibility in the mapping of the associative memory according to the need of application context in an efficient manner. In this respect, several techniques have been investigated and developed in order to solve problems inherent in many previous CAM architectures. Results of tests, allowing the architecture validation using SYMOPSYS tool and FPGA experimental board, are presented.