Reconfigurable Hardware Implementation of CNN Accelerator using Zero-bypass Multiplier

Abstract

Convolutional Neural Networks (CNNs) have undergone accelerated growth due to their capacity to resolve challenging image recognition problems. They are utilized to handle an increasing number of difficulties, such as speech recognition, and the segmentation and categorization of images. The ever-increasing processing needs of CNNs are spawning the market for hardware support strategies. Moreover, CNN workloads are of a streaming nature, which makes them a good choice for reconfigurable hardware architectures like as Field Programmable Gate Arrays (FPGAs). Neural networks are a sort of computer architecture inspired by the way the human brain processes information. A artificial neural network consists of a large number of densely interconnected individual processors, or neurons. By adding a simplified bypass zero multiplier to the neural computing of the system, the proposed system may reduce the processing time and complexity while handling a broad range of datasets. The suggested CNN comprises of two hidden layers and two convolutional layers. The proposed CNN is implemented on a Xilinx zynq 7z020 FPGA using the verilog HDL programming language, with the consideration for space utilization, power estimation, and logical utilization.