TONIC: A timing database for VLSI design

Gregory Schulte, P. Tong, S. Rusu, Stuart Taylor
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Abstract

A unified timing database for VLSI (very large scale integration) design is presented. The approach has been successfully used for the design of a three million transistor microprocessor. The database and timing methodology are oriented towards, but not restricted to, the top-down design style. Emphasis is placed upon integration with other timing tools such as circuit simulators, logic synthesis tools, and static timing analyzers.<>
用于超大规模集成电路设计的时序数据库
提出了一种用于超大规模集成电路(VLSI)设计的统一时序数据库。该方法已成功用于设计300万个晶体管微处理器。数据库和计时方法面向(但不限于)自顶向下的设计风格。重点放在与其他时序工具的集成,如电路模拟器,逻辑合成工具和静态时序分析仪。
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