{"title":"A Serial Communication Protocol for Ultra Dense EEG Networks with Active Electrodes","authors":"Marcelo S Almeida, T. P. Mussolini, T. Pimenta","doi":"10.1109/ICM52667.2021.9664916","DOIUrl":null,"url":null,"abstract":"Electromagnetic interferences found in the hospital environment can alter and/or mask the signals acquired from the skull surface, which are in the range of 10 μV to 100 μV. In order to minimize the interferences, the amplification and signal treatment can be conducted by a circuit placed directly over the electrodes. Besides the traditional electroencephalograms – EEG, our circuit allows the implementation of ultra-dense EEG networks. This article presents the development of a serial bidirectional communication protocol, and its implementation/validation in FPGA.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM52667.2021.9664916","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Electromagnetic interferences found in the hospital environment can alter and/or mask the signals acquired from the skull surface, which are in the range of 10 μV to 100 μV. In order to minimize the interferences, the amplification and signal treatment can be conducted by a circuit placed directly over the electrodes. Besides the traditional electroencephalograms – EEG, our circuit allows the implementation of ultra-dense EEG networks. This article presents the development of a serial bidirectional communication protocol, and its implementation/validation in FPGA.