Implementation of TS De-multiplexer with FPGA in DVB_IP Gateway for Network TV

Abstract

An FPGA-based de-multiplexing architecture is realized in DVB_IP gateway for network TV broadcasting on the dedicated real-time and bandwidth-varying T-bit router, T-bit switch, T-bit transfer (3Tnet) network. The main purpose of this architecture is to convert the multi-program transport stream (MPTS) with bit rate up to 96 Mbps into six single program transport streams (SPTS), which can be encapsulated into real-time transport protocol (RTP) packets in compliance with RFC2250. To prevent loss of presentation synchronization, program clock reference (PCR) correction is implemented in accordance with tolerance defined in ISO/IEC 13818-1. The cooperation between DVB_IP gateway and IP set top box works well and the playout is quite satisfactory