A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement

Abstract

In this paper, a physics based compact model for STT - MRAM is presented which is capable of fast circuit simulation and design space exploration, while enabling the intrinsic device characterization, like transient behavior, effect of thermal noise and Monte-Carlo simulations. The proposed model does not use any technology specific fitting parameters and hence, is fully technology agnostic and scalable. A two-step coupled simulation methodology was developed to account for both the process and initial angle variations, simultaneously. The model has been extensively validated with 22nm FDSOI MRAM hardware data across different PVT corners with less than 4% RMS error. The scalability of the model has further been demonstrated on a state-of-the-art high performance (high speed switching) MTJ stack.