{"title":"Dynamic Reconfigurable PUFs Based on FPGA","authors":"Yijun Cui, Chenghua Wang, Yunpeng Chen, Ziwei Wei, Mengxian Chen, Weiqiang Liu","doi":"10.1109/SiPS47522.2019.9020444","DOIUrl":null,"url":null,"abstract":"Physical unclonable function (PUF) is a promising security primitive. Configurable ring oscillator (CRO) PUF is an evolvement of conventional RO PUF, which improves the entropy and decrease the hardware cost by introducing configurability. Compared with other types of PUF structures, CRO PUFs are FPGA friendly. In this paper, a dynamic reconfigurable mechanism is proposed for the CRO PUF in FPGA implementation. Three different CRO PUFs are implemented using the proposed reconfigurable method and each CRO can be implemented in a single configurable logic block (CLB) of FPGA. Based on the partial reconFigure functions provided by Xilinx FPGAs, the PUF structures can be configured to any of the three PUF structures. The experimental results show that the dynamic reconfigurable PUF structure has a higher hardware efficiency, reliability and stability compared with the previous works.","PeriodicalId":256971,"journal":{"name":"2019 IEEE International Workshop on Signal Processing Systems (SiPS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Workshop on Signal Processing Systems (SiPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SiPS47522.2019.9020444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Physical unclonable function (PUF) is a promising security primitive. Configurable ring oscillator (CRO) PUF is an evolvement of conventional RO PUF, which improves the entropy and decrease the hardware cost by introducing configurability. Compared with other types of PUF structures, CRO PUFs are FPGA friendly. In this paper, a dynamic reconfigurable mechanism is proposed for the CRO PUF in FPGA implementation. Three different CRO PUFs are implemented using the proposed reconfigurable method and each CRO can be implemented in a single configurable logic block (CLB) of FPGA. Based on the partial reconFigure functions provided by Xilinx FPGAs, the PUF structures can be configured to any of the three PUF structures. The experimental results show that the dynamic reconfigurable PUF structure has a higher hardware efficiency, reliability and stability compared with the previous works.