A queuing-theoretic performance model for context-flow system-on-chip platforms

Abstract

Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which prevents the development of effective system-level synthesis techniques. We propose an analytical performance model based on queuing theory for a network-on-chip platform recently reported, which features an extremely simple programming model, while providing superior performance measures when compared with alternative architectures. We developed a multi-processor simulation framework, which can simulate an application at the instruction set level given an architecture configuration, to validate the analytical performance model. The accuracy and applicability of the proposed model is illustrated by two real-life applications, namely an SSL security acceleration processor and MP3 decoder.