A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems

Abstract

This paper presents a 16-channel 14bit 50MS/s ADC designed with a 0.18μm process, used in integrated ultrasound imaging systems. The design considerations of stage resolution distribution are thoroughly discussed. The optimal stage resolution for a 14bit pipelined-SAR is "5-5-6", achieving the best power and area efficiency. According to this, the prototype chip is designed with complete peripheral circuits including LVDS, SPI, bandgap, etc. The measurement results show that this compact design features the highest resolution and SNDR among recent designs with a competitive FoM.