Universal On-Chip Network Simulator for Networks-on-Chip Development

Abstract

This work is devoted to Universal On-Chip Network Simulator (UOCNS) for Network-on-Chip (NoC) development. The principle of the topological approach in NoC design was analyzed. A review of high-level NoC simulators was done. A complete analysis of the structure of UOCNS and its main components was carried out, as well as it was tested on different topologies. A comparison of the simulation results of the same network in UOCNS and in other simulators was made, and the correctness of the model was confirmed.