On Die Clock Tree PSIJ Simplified

Vinod Arjun Huddar
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Abstract

A simplified methodology for On-Die clock tree Power Supply Induced Jitter (PSIJ) analysis is put forth. The approach estimates jitter induced on a clock output (CK) without introducing significant error while significantly reducing simulation times. Approach relies on analysis of various transfer functions of on-die linear regulators. The accuracy of this simplified approach is highly dependent on on-die linear regulator design.
关于模钟树的PSIJ简化
提出了一种简化的模内时钟树电源诱发抖动(PSIJ)分析方法。该方法在不引入显著误差的情况下估计时钟输出(CK)上引起的抖动,同时显著减少了仿真时间。该方法依赖于对模内线性调节器的各种传递函数的分析。这种简化方法的精度高度依赖于模上线性调节器的设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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