Bus-Based and NoC Infrastructure Performance Emulation and Comparison

Abstract

In this paper, we study and compare the performance of bus-based and Mesh-based with Spidernet NoC-based infrastructure in Altera’s FPGA. We first analysis the inner latency performance of the NoC infrastructure among routers, and we provide two modes to emulate the specific application on those infrastructures for the purpose of performance comparison. It is shown that NoC-based infrastructure performs better than bus-based one in terms of latency when the number of flits contained in the packets exceeds certain threshold. In addition, Spidernet-based infrastructure outperforms Mesh-based one under the same condition, which verifies the correctness of the theoretical performance analysis.