Design of Low Power circuit with CMOS Logic using adiabatic technique

Abstract

In VLSI design the role of power consumption is an important concern in our life. The requirement for power reducing techniques is increasing day by day. This paper required CMOS logic family and this technique is called as ADIABATIC switch. The word “adiabatic” is described to conserve energy by the circuit. The adiabatic logic circuit reduces energy in dramatically form. The adiabatic switching and the conventional CMOS logic family are compared to the power dissipation of various parameters. Many research it's to be done by using the adiabatic switching principle. It technique proposed to designs and simulated at 180nm technology by using the Cadence tool.