A sub-2W 10GBase-T analog front-end in 40nm CMOS process

Abstract

The IEEE802.3an 10GBase-T standard [1] provides full duplex transmission and reception over 4 twisted pairs in a 100M UTP cable. Earlier AFE implementations for this standard have utilized a transmitter hybrid configuration requiring multiple DACs with stringent inter-DAC matching requirements [2-3]. This paper describes a new AFE architecture using a single DAC and line-driver to achieve better echo-cancellation linearity. The design achieves >;59dB TX SFDR and >;68dB echo-cancellation (EC) SFDR across 400MHz bandwidth. The AFE receiver circuitry consists of PGA and 2× time-interleaved SHA-less 11b pipelined ADC operating at 800MS/s. Measured receive noise floor and SFDR is <;-144dBm/Hz and >;53dB, respectively. The AFE dissipates less than 2W power, occupies 17mm2 silicon area including 4 lanes with clocking circuitry, and is implemented in a 40nm triple-gate 0.9V/1.2V/2.5V CMOS process.