{"title":"Fault tolerance techniques for avionics wavefront array processors","authors":"R. Duncan","doi":"10.1109/DASC.1990.111312","DOIUrl":null,"url":null,"abstract":"Fault tolerance techniques for wavefront array processing in an avionics environment are analyzed, emphasizing techniques that exploit the wavefront arrays' asynchronous character. Such salient features as array manager software, dedicated fault report and test links, and programmable array module interconnections are proposed. Detection mechanisms for processor and interconnection network faults are discussed. A centralized, asynchronous approach to fault isolation is described. A three-level strategy for fault recovery is examined. First, programmable module interconnections are used for dynamically swapping processor modules from a pool of spares. Second, affected applications migrate to subsystems with spare processing capacity. Finally, applications are replaced with alternative software versions that utilize a faultless, contiguous subset of array module processing nodes.<<ETX>>","PeriodicalId":141205,"journal":{"name":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","volume":"5 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"9th IEEE/AIAA/NASA Conference on Digital Avionics Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DASC.1990.111312","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Fault tolerance techniques for wavefront array processing in an avionics environment are analyzed, emphasizing techniques that exploit the wavefront arrays' asynchronous character. Such salient features as array manager software, dedicated fault report and test links, and programmable array module interconnections are proposed. Detection mechanisms for processor and interconnection network faults are discussed. A centralized, asynchronous approach to fault isolation is described. A three-level strategy for fault recovery is examined. First, programmable module interconnections are used for dynamically swapping processor modules from a pool of spares. Second, affected applications migrate to subsystems with spare processing capacity. Finally, applications are replaced with alternative software versions that utilize a faultless, contiguous subset of array module processing nodes.<>