Implementation of H.264 on TMS320DM642

Abstract

H.264/AVC is the newest video standard to resolve the efficient transmission of video data. Compared to previous generations, it delivers better quality at lower bit rates. However, its computational complexity increases almost exponentially, which is still a problem and has motivated much research into H.264 real-time codec both in industry and academia. H.264 baseline real-time video decoder implementation based on TMS320DM642 and JM86 test code is described in this paper. Firstly, the structure of JM86 is rearranged into three parallel tasks using BIOS multithreading technology. Then, the data structure is redesigned to make full use of the DSP memory and to improve the addressing capability of array and pointer. Finally, lots of time-consuming functions of JM86 are rewritten with assembly language. The system highly speeded up the decoding while maintaining the quality as well. For video sequence of D1 format, the decoding speed reached 25 frames per-second and for CIF format, it reached 60 frames per-second.