Fast saliency map extraction from video: A hardware approach

Amin Moradhasel, Babak Nadjar Araabi, S. M. Fakhraie, M. N. Ahmadabadi
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引用次数: 3

Abstract

Saliency map is a central part of many visual attention systems, particularly during learning and control of bottom-up attention. In this research we developed a hardware tool to extract saliency map from a video sequence. Saliency map is obtained by aggregating primary features of each frame, such as intensity, color, and lines orientation, along with temporal difference. The system is designed to provide both high speed and acceptable accuracy for real-time applications, such as machine vision and robotics. A versatile Verilog model for realization of the video processing system is developed, which can easily be mapped and synthesized on various FPGA or ASIC platforms. The proposed parallel hardware can process over 50 million pixels in a second, which is about 2x faster than the state-of-the-art designs. Experimental results on sample images justify the applicability and efficiency of the developed system in real-time applications.
从视频中快速提取显著性地图:一种硬件方法
显著性图是许多视觉注意系统的核心部分,特别是在自下而上的注意力学习和控制过程中。在这项研究中,我们开发了一个硬件工具,从视频序列中提取显著性地图。显著性图是通过对每帧图像的强度、颜色、线条方向等主要特征以及时间差异进行聚合得到的。该系统旨在为机器视觉和机器人等实时应用提供高速和可接受的精度。开发了一种实现视频处理系统的通用Verilog模型,该模型可以方便地在各种FPGA或ASIC平台上进行映射和合成。提议的并行硬件每秒可以处理超过5000万像素,这比最先进的设计快了大约2倍。样品图像的实验结果验证了系统在实时应用中的适用性和有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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