Representation and robustness for evolved sorting networks

Abstract

We describe evolved sorting networks for a Xilinx 6200 rapidly reconfigurable Field Programmable Gate Array (FPGA) and for a simulated environment. Our goal was to evaluate the efficiency and stability of evolved circuits in a changing environment. Not only did we evolve correct sorting networks, but we also examined the representations of evolved individuals for their runtime efficiency and effectiveness. We compared three different hardware representations: tree structured encodings, linear direct encodings, and raw configuration files. We also used three separate fitness functions. We also present an interesting metric for gate-level resilience to faults: bitwise stability. We find evidence that evolution inherently improves bitwise stability, and that tree structures may confer more bitwise stability than linear structured chromosomes.