Synthesis of orthogonal systolic arrays for fault-tolerant matrix multiplication

Abstract

This paper presents a procedure for designing fault-tolerant systolic array with orthogonal interconnects and bidirectional data flow (2DBOSA) for matrix multiplication. The method employs space-time redundancy to achieve fault-tolerance. The obtained array has Ω = n(n+2) processing elements, and total execution time of Ttot = 6n -5. The array can tolerate single transient errors and the majority of multiple error patterns with high probability. Compared to hexagonal array of same dimensions, the number of I/O pins is reduced for approximately 30%.