Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure

Abstract

This paper presents the first steps towards the implementation of an evolvable and self-adaptable processor cache. The implemented system consists of a run-time reconfigurable memory-to-cache address mapping engine embedded into the split level one cache of a Leon3 SPARC processor as well as of an measurement infrastructure able to profile microarchitectural and custom logic events based on the standard Linux performance measurement interface perf_event. The implementation shows, how reconfiguration of the very basic processor properties, and fine granular profiling of custom logic and integer unit events can be realized and meaningfully used to create an adaptable multi-core embedded system.