Bayesian Training in Photonic Neural Meshes

Abstract

Neural networks based on reconfigurable photonic integrated chips (RPICs) can offer zero-latency processing, marginal power consumption and operational flexibility. On the other hand, they are subject to, performance affecting, operational/fabrication deviations in their building blocks. Here, we present a Bayesian learning framework that when combined with device characterization, can dramatically decrease power consumption beyond 74% and significantly simplify the driving circuitry.