Hardware Design and Optimization of Multimode Pipeline Based FFT for IEEE 802.11ax WLAN Devices

Abstract

In this paper, a new architecture of a multi-mode Fast Fourier Transform hardware for IEEE 802.11ax WLAN standard is presented. The proposed architecture is based on Radix-2 Multipath Delay Commutator (MDC), Radix-22 and Radix 24 Single-path Delay Feedback(SDF) stages. To optimize the throughput and area of the FFT hardware, we applied two design techniques such as compression of redundant twiddle factors, and optimization of twiddle factor multiplication. In FPGA implementation using Altera Stratix IV EP4SGX530KH40C3, the proposed FFT achieved 1.2 GSamples/s throughput and met the requirements of the 802.11ax standard. The synthesis results show that the proposed circuit is 6.19% lower latency and 30.2% lower area compared to a recently presented work while maintaining higher working frequency.