An Analytical Approach to Direct IP Protection of VLSI Floorplans

Abstract

In the DSM VLSI technology, wide-spread design reuse to meet customer's requirements in time enhances the probability of infringement of intellectual property (IP) of VLSI physical design. In design storage or during design transmission between two parties, encryption of a design file is a well-known technique to protect a design against hacking, although it takes significantly long time to encrypt large design files. While encryption basically substitutes and shuffles the bits/ASCII values of a file to conceal the contents of the file, the IP value of a design obtained from optimized partitioning, floorplanning and placement can be protected by redistribution of design elements in the modules and exchanging the locations and orientations of the design modules. As security of design through perturbation exploits the basic properties of physical design, this technique is applicable to protect any intermediate phase, not restricted to binary/ASCII GDSII/OASIS file format only. In this paper, encoding moves for various floorplan representations are analyzed in terms of their time and space requirements. Experimental results on MCNC benchmarks are encouraging.